AT89S51 中英文翻譯

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1、外文原文及中文翻譯 外文原文 AT89S51 The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction se

2、t and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highl

3、y-flexible and cost-effective solution to many embedded control applications. 1. Features： Compatible with MCS.-51 Products 4K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz

4、 to 33 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watch

5、dog Timer Dual Data Pointer Power-off Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode) Green (Pb/Halide-free) Packaging Option 2.Dscription The AT89S51 provides the following standard features:4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watch

6、dog timer, two data pointers, two 16-bit timer/counters, a five-vector two level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectabl

7、e power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware

8、 reset. 3.Pin Description: VCC： Supply voltage (all packages except 42-PDIP). GND： Ground (all packages except 42一PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory). VDD： Supply voltage for the 42-PDIP which connects only the logic core and the emb

9、edded program memory. PWRVDD： Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage. PWRGND： Ground for the 42一PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly conn

10、ected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground. Port 0： Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to p

11、ort 0 pins, the pins can be used as high一impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pull-ups. Port 0 also receives the code bytes during Flash programming and ou

12、tputs the code bytes during program verification. External pull-ups are required during program verification. Port 1： Port 1 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulle

13、d high by the internal pull一ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pull一ups. Port 2： Port 2 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 2 output buffers can sink/sourc

14、e four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pull一ups. Port 2 emits the high-order address byte during fet

15、ches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, Port 2 uses strong internal pull一ups when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function

16、Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3： Port 3 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pi

17、ns, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions

18、of various special features of the AT89S51，as shown in the following table. RST： Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (

19、address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG： Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse i

20、nput (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may beused for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation ca

21、n be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN： Program Store Enable (PSEN

22、) is the read strobe to external program memory. When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP： External Access Enable. EA must be str

23、apped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to Vcc for internal program executions. This pin also receiv

24、es the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1： Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2： Output from the inverting oscillator amplifier 4.Special Function Registers： Note that not all of t

25、he addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1 s to these unlisted locations, since they may be used i

26、n future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register. Dua

27、l Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the

28、DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to "1”during power up. It can be set and rest under software control and is not affected by reset. 5.Me

29、mory Organization： MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. Program Memory： If the EA pin is connected to GND, all program fetches are directed to external mem

30、ory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data Memory： The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessibl

31、e via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. 6.Watchdog Timer (One-time Enabled with Reset-out)： The WDT is intended as a recovery method in situations where the CPU may be subjected

32、 to software upsets. The WDT consists of a 14一bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register (SFR location OA6H). When the WDT is enabled, it will incre

33、ment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RS

34、T pin. 7.Timer 0 and 1： Timer 0 and Timer 1 is a 16-bit Timer/Counter. 8.Interrupts: The AT89S51 has a total of five interrupt vectors:two external interrupts,two timer interrupts,and the serial port interrupt.These interrupts are all shown in Figure 8.1. Each of these interrupt sources can

35、 be individually enabled or disabled by setting or chearing a bit in Special Function Register IE.IE also contains a global disable bit,EA,which disables all interrupts at once. Note that Table 8.1 shows that bit positions IE.6 and IE.5 are unimplemented.User software should not write 1s to these b

36、it positions,since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1,are set at S5P2 of the cycle in which the timers overflow.The values are then polled by the circuitry in the next cycle. Table 8.1:Interrupt Enable(IE) Register Figure 8.1:Interrupt Sources

37、 9.Idle mode: In idle mode ,the CPU puts itself to sleep while all the on-chip peripherals remain active.The mode is invoked by software.The content of the on-chip RAM and all the special function registers remain unchanged during this mode.The idle can be terminated by any enabled interrupt or by

38、 a hardware reset. 中文翻譯 AT89S51 AT89S51是美國(guó)ATMEL公司生產(chǎn)的低功耗，高性能CMOS 8位單片機(jī)，片內(nèi)含4k bytes的可系統(tǒng)編程的Flash只讀程序存儲(chǔ)器，器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)8051指令系統(tǒng)及引腳。它集Flash程序存儲(chǔ)器既可在線編程（ISP)也可用傳統(tǒng)方法進(jìn)行編程及通用8位微處理器于單片芯片中，ATMEL公司的功能強(qiáng)大，低價(jià)位AT89S51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)介，可靈活應(yīng)用于各種控制領(lǐng)域。 1.主要性能參數(shù)：

39、 與MCS-51 產(chǎn)品指令系統(tǒng)完全兼:容 4k字節(jié)在線系統(tǒng)編程(ISP) Flash閃速存儲(chǔ)器 1000次擦寫周期 4. 0---5. 5V的工作電壓范圍 全靜態(tài)工作模式：0Hz---33MHz 三級(jí)程序加密鎖 1288字節(jié)內(nèi)部RAM 32個(gè)可編程I/O口線 2個(gè)16位定時(shí)/計(jì)數(shù)器 6個(gè)中斷源 全雙工串行UART通道 低功耗空閑和掉電模式 中斷可從空閑模式喚醒系統(tǒng) 看門狗(WDT)及雙數(shù)據(jù)指針 掉電標(biāo)識(shí)和快速編程特性 靈活的在線系統(tǒng)編程(ISP一

40、字節(jié)或頁(yè)寫模式) 2.功能特性概述： AT89S51提供以下標(biāo)準(zhǔn)功能：4k字節(jié)Flash閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM， 32個(gè)I/O口線，看門狗（WDT），兩個(gè)數(shù)據(jù)指針，兩個(gè)16位定時(shí)/計(jì)數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89S51可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。 引腳功能說明： 3.引腳功能 Vcc： 電源電

41、壓 GND：地 P0口：P0口是一組8位漏極開路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫‘1’可作為高阻抗輸入端用。 在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址(低8位)和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。 在Flash編程時(shí)，P0 口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。 P1口：P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門電路。對(duì)端口寫‘1’，通過內(nèi)部的上拉電阻把端口拉到

42、高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，囚為內(nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流(In)。 Flash編程和程序校驗(yàn)期間 P 1接收低8位地址。 P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門電路。對(duì)端口寫‘1’，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口，作輸入口使用時(shí)，囚為內(nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流(In)。 在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器(例如執(zhí)行MOVX @DPTR指令)時(shí)，P2口送出高 8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)

43、存儲(chǔ)器(如執(zhí)行MOVX @Ri指令)時(shí)，P2口線卜的內(nèi)容(也即特殊功能寄存器（SFR)區(qū)中P2寄存器的內(nèi)容)，在整個(gè)訪問期間不改變。 Flash編程或校驗(yàn)時(shí)，P2亦接收高位地址和其它控制信號(hào)。 P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口。P3口輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門電路。對(duì)P3 口寫入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時(shí)，被外部拉低的P3 口將用上拉電阻輸出電流（In）。 P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能。 P3 口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。

44、第二功能如下表： P3口引腳 第二功能 P3.0 RXD（串行輸入） P3.1 TXD（串行輸出） P3.2 /INTO（外部中斷0輸入） P3.3 /INT1（外部中斷1輸入） P3.4 T0（定時(shí)/計(jì)數(shù)器0外部輸入） P3.5 T1（定時(shí)/計(jì)數(shù)器1外部輸入） P3.6 /WR（外部數(shù)據(jù)存儲(chǔ)器寫信號(hào)） P3.7 /RD（外部數(shù)據(jù)存儲(chǔ)器讀信號(hào)） RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。WDT溢出將使該引腳輸出高電平，設(shè)置SFR AUXR 的DISRTO位（地址8EH）可打開或關(guān)閉該功能。DISRTO位缺省為RE

45、SET輸出高電平打開狀態(tài)。 ALE/PROG：當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE(地址鎖存允許)輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE仍以時(shí)鐘振蕩頻率的1/6輸出固定的正脈沖信號(hào)，囚此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖。 對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（PROG）。 如有必要，可通過對(duì)特殊功能寄存器（SFR)區(qū)中的8EH單元的D0位置位，可禁正ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE

46、無(wú)效。 PSEN：程序儲(chǔ)存允許(PSEN)輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89S51由外部程序存儲(chǔ)器取指令(或數(shù)據(jù))時(shí)，每個(gè)機(jī)器周期兩次PSEN有效，即輸出兩個(gè)脈沖。當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器，沒有兩次有效的PSEN信號(hào)。 EA/VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲(chǔ)器(地址為0000H-FFFFH), EA端必須保持低電平(接地)。需注意的是：如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。 如EA端為高電平(接Vcc端)，CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。 Flash存儲(chǔ)器編程時(shí)，該引腳加上+12 V的編程電壓Vpp。 XTAL 1：振

47、蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。 XTAL2：振蕩器反相放大器的輸出端。 4.特殊功能寄存器： 特殊功能寄存器的于片內(nèi)的空間分布的這些地址并沒有全部占用，沒有占用的地址亦不可使用，讀這些地址將得到一個(gè)隨意的數(shù)值。而寫這些地址單元將不能得到預(yù)期的結(jié)果。 中斷寄存器： 各中斷允許控制位于IE寄存器，5個(gè)中斷源的中斷優(yōu)先級(jí)控制位于IP寄存器。 雙時(shí)鐘指針寄存器： 為更方便地訪問內(nèi)部和外部數(shù)據(jù)存儲(chǔ)器，提供了兩個(gè)16位數(shù)據(jù)指針寄存器：DP0位于SFR(特殊功能寄存器)區(qū)塊中的地址82H, 83H和DP1位于地址84H, 85H，當(dāng)SFR

48、中的位DPS=0選擇DP0，而DPS=1則選擇DP1。用戶應(yīng)在訪問相應(yīng)的數(shù)據(jù)指針寄存器前初始化DPS位。 電源空閑標(biāo)志： 電源空閑標(biāo)志（POF）在特殊功能寄存器SFR中PCON的第4位(PCON.4)，電源打開時(shí)POF置‘1’，它可由軟件設(shè)置睡眠狀態(tài)并不為復(fù)位所影響。 5.存儲(chǔ)器： 51系列單片機(jī)的程序和數(shù)據(jù)存儲(chǔ)器具有獨(dú)立的地址空間，最大有64K字節(jié)的外部程序和數(shù)據(jù)存儲(chǔ)器。 程序存儲(chǔ)器： 如果EA引腳接地(GND)，全部程序均執(zhí)行外部存儲(chǔ)器。 在AT89S51,假如EA接至Vcc(電源+)，程序首先執(zhí)行地址從0000H-OFFFH （4KB）內(nèi)部程序存儲(chǔ)器

49、，而執(zhí)行地址為1000H-FFFFH (60KB)的外部程序存儲(chǔ)器。 數(shù)據(jù)存儲(chǔ)器： AT89S51的具有128字節(jié)的內(nèi)部RAM，這128字節(jié)可利用直接或間接尋址方式訪問，堆棧操作可利用間接尋址方式進(jìn)行，128字節(jié)均可設(shè)置為堆棧區(qū)空間。 6.看門狗定時(shí)器(WDT)： WDT是為了解決CPU程序運(yùn)行時(shí)可能進(jìn)入混亂或死循環(huán)而設(shè)置，它由一個(gè)14bit計(jì)數(shù)器和看門狗復(fù)位SFR (WDTRST)構(gòu)成。外部復(fù)位時(shí)，WDT默認(rèn)為關(guān)閉狀態(tài)，要打開WDT，用戶必須按順序?qū)?1EH和0E1H寫到WDTRST寄存器（SFR地址為OA6H},當(dāng)啟動(dòng)了WDT，它會(huì)隨晶體振蕩器在每個(gè)機(jī)器周期計(jì)數(shù)，除

50、硬件復(fù)位或WDT溢出復(fù)位外沒有其它方法關(guān)閉WDT，當(dāng)WDT溢出，將使RSF引腳輸出高電平的復(fù)位脈沖。 7.定時(shí)器0和定時(shí)器1： 定時(shí)器0和1都是16位定時(shí)/計(jì)數(shù)器。 8.中斷： AT89S51具有的五個(gè)中斷源：兩個(gè)外部中斷，兩個(gè)定時(shí)器中斷，一個(gè)串口中斷，如圖8.1所示。 這些中斷源的每一個(gè)都可以通過設(shè)置特殊功能寄存器IE啟用或禁用，IE還包含了一個(gè)全局禁止位EA，它可一次禁止所有的中斷。 請(qǐng)注意，表8.1中位IE.6和IE.5是保留位，它們可能會(huì)在未來(lái)的AT89產(chǎn)品中使用。 表8.1：中斷允許寄存器 （MSB） (LSB) EA - - ES ET1

51、 EX1 ET0 EX0 中斷允許位=1，允許中斷；中斷允許位=0，不允許中斷。 EA IE.7 總中斷允許控制位 - IE.6 保留 - IE.5 保留 ES IE.4 串行口中斷允許控制位 ET1 IE.3 定時(shí)/計(jì)數(shù)器1的中斷允許控制位 EX1 IE.2 外部中斷1的中斷允許控制位 ET0 IE.1 定時(shí)/計(jì)數(shù)器0的中斷允許控制位 EX0 IE.0 外部中斷0中斷允許控制位 圖8.1.：中斷源 9.空閑模式： 在空閑模式下，CPU使自己進(jìn)入睡眠狀態(tài)，而所有片上外設(shè)仍然工作.此模式由軟件觸發(fā)，片內(nèi)RAM和特殊功能寄存器的所有內(nèi)容保持不變.此模式可被任何使能中斷或硬件復(fù)位終止。